Clock Tree Synthesis#
The clock tree synthesis module in OpenROAD (cts
) is based on TritonCTS
2.0. It is available from the clock_tree_synthesis
command. TritonCTS 2.0
performs on-the-fly characterization. Thus, there is no need to generate
characterization data. The on-the-fly characterization feature can be optionally
controlled by parameters specified by the configure_cts_characterization
command. Use set_wire_rc
command to set the clock routing layer.
Commands#
Note
Parameters in square brackets
[-param param]
are optional.Parameters without square brackets
-param2 param2
are required.
Configure CTS Characterization#
configure_cts_characterization
[-max_slew max_slew]
[-max_cap max_cap]
[-slew_steps slew_steps]
[-cap_steps cap_steps]
Options#
Switch Name |
Description |
---|---|
|
Max slew value (in the current time unit) that the characterization will test. If this parameter is omitted, the code would use max slew value for specified buffer in |
|
Max capacitance value (in the current capacitance unit) that the characterization will test. If this parameter is omitted, the code would use max cap value for specified buffer in |
|
Number of steps that |
|
Number of steps that |
Clock Tree Synthesis#
clock_tree_synthesis
-buf_list <list_of_buffers>
[-root_buf root_buf]
[-wire_unit wire_unit]
[-clk_nets <list_of_clk_nets>]
[-distance_between_buffers]
[-branching_point_buffers_distance]
[-clustering_exponent]
[-clustering_unbalance_ratio]
[-sink_clustering_enable]
[-sink_clustering_size cluster_size]
[-sink_clustering_max_diameter max_diameter]
[-balance_levels]
[-num_static_layers]
[-sink_clustering_buffer]
[-use_dummy_load]
[-insertion_delay]
[-sink_buffer_max_cap_derate derate_value]
[-delay_buffer_derate derate_value]
Options#
Switch Name |
Description |
---|---|
|
Tcl list of master cells (buffers) that will be considered when making the wire segments (e.g. |
|
The master cell of the buffer that serves as root for the clock tree. If this parameter is omitted, the first master cell from |
|
Minimum unit distance between buffers for a specific wire. If this parameter is omitted, the code gets the value from ten times the height of |
|
String containing the names of the clock roots. If this parameter is omitted, |
|
Distance (in microns) between buffers that |
|
Distance (in microns) that a branch has to have in order for a buffer to be inserted on a branch end-point. This requires the |
|
Value that determines the power used on the difference between sink and means on the CKMeans clustering algorithm. The default value is |
|
Value determines each cluster’s maximum capacity during CKMeans. A value of |
|
Enables pre-clustering of sinks to create one level of sub-tree before building H-tree. Each cluster is driven by buffer which becomes end point of H-tree structure. |
|
Specifies the maximum number of sinks per cluster. The default value is |
|
Specifies maximum diameter (in microns) of sink cluster. The default value is |
|
Attempt to keep a similar number of levels in the clock tree across non-register cells (e.g., clock-gate or inverter). The default value is |
|
String containing the names of the clock roots. If this parameter is omitted, |
|
Set the number of static layers. The default value is |
|
Set the sink clustering buffer(s) to be used. |
|
Enables obstruction-aware buffering such that clock buffers are not placed on top of blockages or hard macros. This option may reduce legalizer displacement, leading to better latency, skew or timing QoR. The default value is |
|
Applies 2X spacing non-default rule to all clock nets except leaf-level nets. The default value is |
|
Don’t consider insertion delays in macro timing models in balancing latencies between macro cells and registers. This option prevents construction of separate clock trees for macro cells and registers. The default value is |
|
Applies dummy buffer or inverter cells at clock tree leaves to balance loads. The default values is |
|
Use this option to control automatic buffer selection. To favor strong(weak) drive strength buffers use a small(large) value. The default value is |
|
This option is used with -insertion_delay option that balances latencies between macro cells and registers by inserting delay buffers. The default values is |
Report CTS#
Another command available from cts
is report_cts
. It is used to
extract metrics after a successful clock_tree_synthesis
run. These are:
Number of Clock Roots
Number of Buffers Inserted
Number of Clock Subnets
Number of Sinks.
report_cts
[-out_file file]
Options#
Switch Name |
Description |
---|---|
|
The file to save |
Useful Developer Commands#
If you are a developer, you might find these useful. More details can be found in the source file or the swig file.
Command Name |
Description |
---|---|
|
Option to plot the CTS to GUI. |
Example scripts#
clock_tree_synthesis -root_buf "BUF_X4" \
-buf_list "BUF_X4" \
-wire_unit 20
report_cts "file.txt"
Regression tests#
There are a set of regression tests in ./test
. For more information, refer to this section.
Simply run the following script:
./test/regression
Limitations#
FAQs#
Check out GitHub discussion about this tool.
References#
License#
BSD 3-Clause License. See LICENSE file.