RAM Generator

RAM Generator#

⚠️ This is an experimental module currently under development. See #9392. ⚠️

The Random Access Memory generator module in OpenROAD (ram) is inspired by the DFFRAM project from AUCOHL. This module is designed to create dense memory arrays from standard cells when other memory compilers are not available. Given a standard cell library with the required basic cells, the generator can produce a placed and routed RAM block. The generated ram can be checked using the built-in static timing analyzer rather than SPICE simulation, leading to faster turnaround time.

Major Features:

  • Support for 1rw, 1rw1r, 1r1w, 2r1w memories

  • Arbitrary word size and number of words (although timing must be checked)

  • Arbitrary word mask granularity

  • Generated behavioral Verilog model for fast, portable simulation

Tested Platforms:

  • sky130hd

  • Nangate45

Planned Features:

Commands#

Note

  • Parameters in square brackets [-param param] are optional.

  • Parameters without square brackets -param2 param2 are required.

RAM Generation#

The generate_ram command is an all-in-one command to place and route a RAM. Standard cell libraries must be loaded before running this command. The module will create a new design, therefore a design should not be loaded before running the command.

generate_ram [-mask_size bits]
             -word_size bits
             -num_words words
             [-rw_ports count]
             [-r_ports count]
             [-w_ports count]
             [-column_mux_ratio ratio]
             [-storage_cell name]
             [-tristate_cell name]
             [-inv_cell name]
             [-power_net_name name]
             [-ground_net_name name]
             -routing_layer config
             -ver_layer config
             -hor_layer config
             -filler_cells fillers
             [-tapcell name]
             [-max_tap_dist value]
             [-write_behavioral_verilog filename]

Options#

Switch Name

Description

-mask_size

Determines the number of bits which are grouped together for masking during writes. For example, a mask size of 8 will enable each 8 bits of the word to be masked when writing (commonly known as byte masking). A mask size of 1 will enable each bit to be individually masked. The write enable signal for each port will be (word_size / mask_size) bits wide. The word size must be a multiple of the mask size. Default: equal to -word_size.

-word_size

Size of each word in bits.

-num_words

Number of words in the array.

-rw_ports

Number of read-write ports for the array. Sum of read-write ports and write ports must equal 1. Default: 1.

-r_ports

Number of read ports for the array. Default: 0.

-w_ports

Number of write ports for the array. Sum of read-write ports and write ports must equal 1. Default: 0.

-column_mux_ratio

Number of words sharing a physical column. Must be 1, 2, or 4. The number of words must be divisible by the column mux ratio. Default: 1 (no column muxing).

-storage_cell

Name of the master to use for the storage device (i.e. a flip-flop). Must be positive-edge triggered. Default: auto-select from the loaded cell library.

-tristate_cell

Name of the master to use for the tristate device (i.e. a tristate inverter). It is currently assumed that the device is inverting. Default: auto-select from the loaded cell library.

-inv_cell

Name of the master to use for inverters. Default: auto-select from the loaded cell library.

-routing_layer

A list of the metal layer and metal width (in microns) for generating standard cell power tracks (followpins). Example: {met1 0.48}.

-power_net_name

Name of the power net to create. Default: VDD.

-ground_net_name

Name of the ground net to create. Default: VSS.

-ver_layer

A list of the metal layer, metal width (in microns), and metal pitch (in microns) for generating power grid stripes on the first vertical layer above the followpin layer. Example: {met2 0.48 40}. North/South I/O pins are also created in this layer.

-hor_layer

A list of the metal layer, metal width (in microns), and metal pitch (in microns) for generating power grid stripes on the first horizontal layer above the followpin layer. Example: {met3 0.48 40}. East/West I/O pins are also created in this layer.

-filler_cells

A list of filler cells to use. Example: {FILL_X1 FILL_X2 FILL_X4}.

-tapcell

The name of the tapcell master to insert into the grid to obey latchup requirements. Requires -max_tap_dist. If this argument is not provided, no tapcells will be inserted.

-max_tap_dist

The distance (in microns) that tapcells should be placed apart. Requires -tapcell.

-use_latch

If set to 1, uses a two-phase latch-based design instead of flip-flops for the storage elements. Functionally equivalent to flip-flop design with smaller storage cell area. Default: 0.

-write_behavioral_verilog

Write a behavioral Verilog model of the RAM array to the specified file.

Example scripts#

See test/make_8x8.tcl.

Regression tests#

There are a set of regression tests in ./test. Refer to this section for more information.

Simply run the following script:

./test/regression

Limitations#

This is an experimental module and many basic features may not work yet. Please see #9392 for ongoing and future work.

FAQs#

Check out GitHub discussion about this tool.

Authors#

References#

Inspired by the DFFRAM project from AUCOHL.

License#

BSD 3-Clause License. See LICENSE file.

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